1. Field of the Invention
The present invention relates to a structure of a nonvolatile semiconductor memory device, and more particularly to a structure of a flash memory using an SOI (Silicon On Insulator) substrate. The present invention also relates to a semiconductor integrated circuit such as an LSI in which the nonvolatile semiconductor memory device is formed.
2. Description of the Background Art
FIG. 46 is a cross section schematically showing a structure of a memory cell transistor in a flash memory using a bulk substrate (which refers to an ordinary semiconductor substrate, not an SOI substrate). In an upper surface of a silicon substrate 101, a source region 102s and a drain region 102d which are paired are formed away from each other. On the upper surface of the silicon substrate 101 in a portion between the source region 102s and the drain region 102d formed is a multilayer structure in which a gate oxide film 103, a floating gate 104, an insulating film 105 and a control gate 106 are layered in this order. On a side surface of the multilayer structure, a sidewall 107 is formed of the insulating film.
In a write operation of data, a high voltage is applied to the drain region 102d and the control gate 106 with a ground potential applied to the source region 102s, for example. Through this application, hot electrons generated in a high-field region near a channel region and the drain region 102d are implanted into the floating gate 104.
FIG. 47 is a cross section schematically showing a structure of a memory cell transistor in a flash memory using the SOI substrate. An SOI substrate 108 has a multilayer structure in which a silicon substrate 109, a BOX (Buried Oxide) layer 110 and a silicon layer 111 are layered in this order. In the silicon layer 111, a full-isolation insulating film 112 extending from an upper surface of the silicon layer 111 to reach an upper surface of the BOX layer 110 is selectively formed. In an element formation region defined by the isolation insulating film 112, the paired source region 102s and drain region 102d are formed away from each other. A bottom surface of the source region 102s and that of the drain region 102d reach the upper surface of the BOX layer 110.
Further, on the upper surface of a body region, that is, the silicon layer 111 in a portion between the source region 102s and the drain region 102d formed is the multilayer structure in which the gate oxide film 103, the floating gate 104, the insulating film 105 and the control gate 106 are layered in this order. On the side surface of the multilayer structure, the sidewall 107 is formed of the insulating film.
FIG. 48 is a circuit diagram showing part of a configuration of a memory cell array in the flash memory. FIG. 48 shows a configuration consisting of only fifteen memory cells in a matrix with five rows and three columns. Each memory cell comprises the memory cell transistor shown in FIG. 47. The control gates CG of the memory cell transistors in the memory cells belonging to a row are connected to a common word line. For example, the control gates CG of the memory cell transistors in the memory cells MC11 to MC13 are connected in common to a word line WL101.
Further, sources S of the memory cell transistors in the memory cells belonging to a row are connected to a common source line. For example, the sources S of the memory cell transistors in the memory cells MC11 to MC13 are connected in common to a source line SL101. Respective source lines SL101 to SL105 in the rows are connected to a common source line SL100.
Furthermore, drains D of the memory cell transistors in the memory cells belonging to a column are connected to a common bit line. For example, the drains D of the memory cell transistors in the memory cells MC11 to MC51 are connected in common to a bit line BL101.
FIG. 49 is a plan view showing a structure of the background-art nonvolatile semiconductor memory device using the configuration of the memory cell array shown in FIG. 48. In FIG. 49, an arrangement of the floating gate, the word line (also used as the control gate), the source line and the isolation insulating film is schematically shown. For example, floating gates 411, 412, and 421 shown in FIG. 49 correspond to the respective floating gates FG in the memory cell transistors of the memory cells MC11, MC12, MC21 shown in FIG. 48.
Further, for example, a source region Sa shown in FIG. 49 corresponds to the respective sources S in the memory cell transistors of the memory cells MC11 and MC21 shown in FIG. 48, and a source region Sd shown in FIG. 49 corresponds to the respective sources S in the memory cell transistors of the memory cells MC31 and MC41 shown in FIG. 48.
Furthermore, for example, a drain region Da shown in FIG. 49 corresponds to the respective drains D in the memory cell transistors of the memory cells MC21 and MC31 shown in FIG. 48, and a drain region Dd shown in FIG. 49 corresponds to the respective drains D in the memory cell transistors of the memory cells MC41 and MC51 shown in FIG. 48.
Referring to FIG. 49, the source lines SL101 and SL102 include the source regions Sa to Sc, the source lines SL103 and SL104 include the source regions Sd to Sf, and the source line SL105 includes the source regions Sg to Si. Each of the source lines SL101 to SL105 is formed by providing a region where no isolation insulating film 112 is formed between the rows.
FIG. 50 is a cross section showing a cross-sectional structure taken along the line X100 of FIG. 49. The source region Sa and the source region Sb are isolated from each other by the full-isolation insulating film 112.
This background-art nonvolatile semiconductor memory device, however, has the following problem. Referring to FIG. 47, this problem will be discussed. As discussed above, in the write operation of data, a high voltage is applied to the drain region 102d and the control gate 106 with a ground potential applied to the source region 102s. At this time, a large number of pairs of electrons and positive holes are generated near the channel region and the drain region 102d through an collision ionization.
In the background-art nonvolatile semiconductor memory device using the SOI substrate, since the body region is in an electrically floating state, the positive holes are accumulated in the body region. Therefore, as the body potential rises, a parasitic bipolar transistor consisting of the source region 102s, the drain region 102d and the body region is driven and as a result, a parasitic bipolar current is carried from the source region 102s towards the drain region 102d, to cause a malfunction. Thus, in the background-art nonvolatile semiconductor memory device, the positive holes are accumulated in the body region due to the electrically floating state of the body region, to drive the parasitic bipolar transistor, thereby disadvantageously causing a malfunction.